The present invention relates to semiconductor integrated circuits having a protection device and methods for manufacturing same.
In semiconductor integrated circuits, there is a problem with electrostatic destruction. This known phenomena results in gate oxide film destruction or PN junction destruction of the inner circuit due to static electricity applied to the chip through pins of the package while in handling.
Conventionally, a signal input pad is connected to the inner circuit of an integrated circuit chip through an input protection resistor of about 1 K.OMEGA., which is made from poly-Si, and a PN junction. This protection circuit acts to lower the peak electric potential with the protection resistor, and to release electric charge buildup to the substrate with the PN junction acting as a diode. Accordingly, the voltage and the amount of charge applied to the inner circuit are reduced. However, in connection with the output pad, if a resistor having a resistivity on the order of about 1 K.OMEGA. is used, output delays occur because of the capacity of the load applied to the chip. This means that the access time of integrated circuits such as DRAMs is delayed. Hence, there is a disincentive to connect a resistor having large resistivity to the output pad. This results in a lowering of the withstand voltage, thereby leading to an increased incidence of electrostatic destruction.
FIG. 1 shows a protection device of a conventional integrated circuit. A wire 1 of A1 is shown extending to the output pad and another wire 2 (A1) is connected to the inner circuit. Wires 1 and 2 each contact an n.sup.+ -region 3 formed on a p.sup.- -type substrate.
The destruction described above tends to arise at the contact between A1 wire 1 and n.sup.+ -region 3, and especially tends to occur at the corner denoted by the reference character A. The cause is junction destruction produced by the electric field concentration.